The present invention relates generally to active-type planar lightwave circuits. More particularly, the present invention relates to a method for depositing precise metallization areas for refractive index control in active-type of planar lightwave circuits.
Planar lightwave circuits comprise fundamental building blocks for the modern fiber optic communications infrastructure. Planar lightwave circuits (PLCs) are generally devices configured to transmit light in a manner analogous to the transmission of electrical currents in printed circuit boards and integrated circuit devices. Examples include arrayed waveguide grating devices, integrated wavelength multiplexers/demultiplexers, optical switches, optical modulators, wavelength-independent optical couplers, and the like.
PLCs generally involve the provisioning of a series of embedded optical waveguides upon a semiconductor substrate, with the optical waveguides fabricated from a silica glass. Planar lightwave circuits are constructed using the advanced tools and technologies developed by the semiconductor industry. Modern semiconductor electronics fabrication technology can aggressively address the increasing need for integration currently being used to make PLCs. By using manufacturing techniques closely related to those employed for silicon integrated circuits, a variety of optical elements can be placed and interconnected on the surface of a silicon wafer or similar substrate. This technology has only recently emerged and is advancing rapidly with leverage from the more mature tools of the semiconductor-processing industry.
PLCs are constructed with a number of waveguides precisely fabricated and laid out across a silicon wafer. A conventional optical waveguide comprises an un-doped silica bottom clad layer, with at least one waveguide core formed thereon, and a cladding layer covering the waveguide core, wherein a certain amount of at least one dopant is added to both the waveguide core and the cladding layer so that the refractive index of the waveguide core is higher than that of the cladding layer. Fabrication of conventional optical waveguides involves the formation of a silica layer as the bottom clad (BC), usually grown by thermal oxidation, or flame hydrolysis deposition (FHD), upon a silicon semiconductor wafer. The core layer is a doped silica layer, which is deposited by either plasma-enhanced chemical vapor deposition (PECVD) or FHD. An annealing procedure then is applied to this core layer (heated above 1000 C.). The waveguide pattern is subsequently defined by photolithography on the core layer, and reactive ion etching (RIE) is used to remove the excess doped silica to form one or more waveguide cores. A top cladding layer is then formed through a subsequent deposition process. Finally, the wafer is cut into multiple planar lightwave circuit dies and packaged according to their particular applications.
Prior art FIG. 1 shows a cross-section view of two planar optical waveguides of a conventional PLC. As depicted in FIG. 1, the planar optical waveguides include two doped SiO2 glass cores 10a-10b formed over a SiO2 bottom cladding layer 12 which is on a silicon substrate 13. A SiO2 top cladding layer 11 covers both the cores 10a-b and the bottom cladding layer 12. As described above, the refractive index of the cores 10a-b is higher than that of top cladding layer 11 and the bottom clad 12. Consequently, optical signals are confined axially within cores 10a-b and propagate lengthwise through cores 10a-b. 
PLC devices having multiple cores comprise the basic building blocks of active type optical devices. One such increasingly important optical device is an optical switch. As optical communications networks become more complex and carry more data traffic, optical switches play an increasingly important role. Optical switches play an increasingly important role as today""s optical networks become more complex and carry more capacity. Optical switches can be deployed in applications such as network protection and restoration and dynamically reconfigurable add/drop modules. Although several switching technologies are available (e.g., opto-mechanical type switches, liquid crystal, etc.), PLC based thermo-optic switches, where light is guided in planar waveguides, is emerging as reliable technology of choice.
PLC based thermo-optic switches utilize materials such as silica or polymers which exhibit the xe2x80x9cthermo-optic effectxe2x80x9d, wherein their refractive indices change as their temperature is changed. This thermo-optic coefficient could either be positive like silica (approximately 10xe2x88x925/xc2x0 C.) or negative like polyimide (approximately 10xe2x88x924/xc2x0 C.). This type of switch is fast enough for protection and restoration purposes, compact, and well suited for integration with other PLC components, such as arrayed waveguide gratings, to form more complicated modules like an optical add/drop multiplexers. These thermo-optic effect based devices have been used in a variety of systems, such as, for example, optical switches, variable optical attenuators (VOAs), dynamic gain flattening filters (DGFF), and integrated devices such as a VMUX (VOA plus MUX).
Prior art FIG. 2 shows a diagram of a Mach-Zehnder thermo-optic switch. As depicted in FIG. 2, a first waveguide (core 10a) and a second waveguide (core 10b) are used to implement input ports (e.g., Pin1 and Pin2) and output ports (e.g., Pout1 and Pout2) as shown. The first and second waveguides pass through a first coupling region 21 and a second coupling region 22. A resistive thin film heater is deposited above each waveguide between the two coupling regions 21-22 (e.g., heater1 and heater2).
The heaters are used to selectively heat one waveguide core or the other to change its refractive index, and thereby modulate an accumulated phase difference of light propagating through the two waveguide cores 10a-b. When light is launched into one of the input ports, it is split into the two cores 10a-b by the first coupler 21 with equal optical power and xc2xd phase difference. As light travels through the waveguide cores 10a-b, the phase difference can be altered using a temperature difference between the two cores, as controlled by the two heaters. After passing through the second coupler 22, the two beams recombine either constructively or destructively at either of the two output ports, depending upon the exact phase difference between the two cores 10a-b. The exact phase difference is controlled by precisely controlling the current/voltage applied to the heaters. This modulation of temperature achieves the purpose of switching the light between the two output ports. The electrical power needed to switch each path is typically on the order of a few hundred milliwatts. Switches can also be cascaded for added extinction ratio without sacrificing much on insertion loss. The same technique can be used in VOA devices and other types of thermo-optic active PLC devices.
There exists problems with the prior art metallization process for the above described types of thermo-optic PLC devices. Different metals are chosen for heater and interconnect due to the different conductivity requirements for each layer. One must be capable of etching these differing metals without adversely affecting the other. These metals must be in contact with each other, which drives the requirement for highly selective etch processes. Ideally, those processes in which one layer etches readily and the other not at all. Adhesion of the two materials must be maintained. Many prior art thermo-optic PLC devices utilize chrome as the heater material and gold as the interconnect material. A chrome wet etch process requires special disposal due to the heavy metal content. Thus, the chrome wet etch process is thus overly expensive and time-consuming. Both gold and chrome can be dry etched using chlorine. The etchers designed to handle the corrosive chlorine gas can be complex and expensive. One must etch the interconnect without attacking the heater layer. Conversely, one must etch the heater without attacking the interconnect layer. High selectivity between gold and chrome and the photolithography mask is difficult to achieve with a chlorine dry etch process.
Gold is difficult to work with due to the fact that there tend to be adhesion problems (e.g., between gold and silica and between gold and chrome). Gold typically requires an adhesion layer to ensure its integrity. Prior art attempts to use gold interconnects on nickel thin film heaters were not effective in solving the adhesion problems. Even when combined with nickel heaters, the gold tends to xe2x80x9cpeelxe2x80x9d during wet etch patterning.
Another problem involves interconnect alignment during patterning and etching of the overlying layer. During prior art gold/chrome processes, gold and chrome metal layers are typically deposited and patterned separately. However, alignment of the overlying elements from the overlying layer is critical. For example, in a case where the underlying layer is used to pattern and form the heater (e.g., chrome) in one deposition/etch process, it is critical that the overlying layer (e.g., gold) is deposited, patterned, and etched such that the interconnects are in the correct location with respect to the heaters. This precise alignment can be difficult to attain.
In another prior art method, the interconnect and heater patterns are deposited and etched at the same time. This method requires a photolithographic mask that has sufficient selectivity to withstand both etches. There is the added disadvantage of requiring good line width control during both metal etches. A second masking and etch step is needed to remove the conductive layer from the heater region. Thus, alignment is critical for both masking steps.
Thus what is required is a solution that eliminates fabrication problems involved in working with chrome and gold in PLC device fabrication. What is required is a solution that eliminates interconnect alignment problems in the fabrication of PLC devices. What is further required is a solution that increases the yield and reliability of active thermo-optic PLC devices. The present invention provides a novel solution to the above requirements.
The present invention is an active device metallization process that eliminates PLC fabrication problems involved in working with chrome and gold in PLC device fabrication. The present invention provides a solution that eliminates interconnect alignment problems in the fabrication of PLC devices. The present invention provides a solution that reduces the number of critical dimensions. The present invention provides a solution that improves adhesion of the interconnect layer. The present invention provides a solution that increases the yield and reliability of active thermo-optic PLC devices.
In one embodiment, the present invention is implemented as an active device metallization process for making resistive heaters for a planar lightwave circuits. The process includes the step of depositing a resistive layer on a top clad of a planar lightwave circuit. An interconnect layer is subsequently deposited over the resistive layer. In this embodiment, tungsten is used for the resistive layer and aluminum is used for the interconnect layer. The both heater and interconnect layers are deposited across the entire surface of the PLC wafer sequentially. The interconnect layer is then patterned (e.g., masked using photolithography techniques) and etched to define a heater interconnect over the resistive layer. The heater interconnect is then masked, and the resistive layer is etched to define a resistive heater. Thus, both the resistive layer and the interconnect layer can be deposited prior to the patterning and etching steps.
The heater interconnect is disposed entirely over the resistive heater, and has a smaller width than the resistive heater such that a portion of the resistive heater is exposed entirely around the periphery of the heater interconnect. The heater interconnect is defined to include a xe2x80x9cheater conduct regionxe2x80x9d between a first contact pad and a second contact pad such that a current between the first contact pad and the second contact pad is conducted through the heater conduct region of the resistive heater, thereby generating heat which is conducted into the top clad of the PLC. The heater conduct region is located on the top clad above the core.
The difference between the smaller width of the heater interconnect and the larger width of the underlying resistive heater is sized to be sufficiently large to decrease an alignment sensitivity of the lithography process for patterning the heater interconnect. The resistive heater is essentially an xe2x80x9coversizexe2x80x9d version of the heater interconnect. Thus the only critical alignment is that of the heater conduct region with respect to the underlying waveguide core. This eliminates the interconnect alignment problems of the prior art fabrication processes.
Similarly, the only critical dimension is the width of the heater conduct region. Hence, the only line width that is critical to control is the heater conduct region line width.
A dry etch process can be used to etch the aluminum interconnect layer and/or the tungsten resistive layer. The dry etch process can be a reactive ion etching process. A wet etch process can be used to etch the aluminum interconnect layer. For either wet or dry processes wherein the aluminum etch does not attack the tungsten. Both the dry and wet etch processes are less expensive and less time-consuming than the prior art etch processes for chrome and gold. Chemicals involved in the etching of aluminum and tungsten are much less hazardous than those involved with the etching of chrome. This eliminates the prior art problems from working with chrome and gold in PLC device fabrication.